library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity tb_quadrature is
end tb_quadrature;

architecture structure of tb_quadrature is
	component quadrature
		port (
		clock: in std_logic;
        reset: in std_logic;
		channelA: in std_logic;
		channelB: in std_logic;
		count: out std_logic_vector(10 downto 0)
		);
	end component;
	
    signal channelA, channelB : std_logic;
	signal count: std_logic_vector(10 downto 0);
    signal clock : std_ulogic := '0';
	signal reset : std_ulogic := '0';
    signal output: signed(10 downto 0);
begin
	duv: quadrature
		port map (clock=>clock, reset=>reset, channelA=>channelA, channelB=>channelB, count=>count);

    clock <= not clock after 10 ns;
	reset <= '0', '1' after 40 ns;
	
	seq: process
	begin
        channelA <= '0';
		channelB <= '0';
		wait for 40 ns;
		
		for i in 1 downto 0 loop
			channelA <= '1';
			wait for 40 ns;
			channelB <= '1';
			wait for 40 ns;
			channelA <= '0';
			wait for 40 ns;
			channelB <= '0';
			wait for 40 ns;
		end loop;
		
		for i in 2 downto 0 loop
			channelB <= '1';
			wait for 40 ns;
			channelA <= '1';
			wait for 40 ns;
			channelB <= '0';
			wait for 40 ns;
			channelA <= '0';
			wait for 40 ns;
		end loop;
		
		wait;
	end process;
	
	output <= signed(count);
	
end structure;

